IOE Computer Organization and Architecture 2072 Chaitra Regular Exam Question Solution.

1.

Define computer architecture and computer organization. How can we maintain a performance balance between processor and memory? Discuss the limitations of using single bus system to connect different devices in any given system.

[2+2+2]

2.

What do you mean by instruction format? Write code for given operation using 3,2,1 and 0 address instruction format. 

X=(A-B*F)*C+D/E. 

[4+8] 

3 ADDRESS INSTRUCTION FORMAT

MUL R1,B,F 

SUB R2,A,R1

MUL R1,R2,C

DIV R2,D,E

ADD X,R1,R2 

2 ADDRESS INSTRUCTION FORMAT

MOV R1,B

MUL R1,F 

MOV R2,A

SUB R2,R1

MUL R2,C

MOV R1,D

DIV R1,E

ADD R1,R2

M0V X,R1 

1 ADDRESS INSTRUCTION FORMAT

LOAD B

MUL F

STORE T1

LOAD A

SUB T1

MUL C

STORE T2

LOAD E

DIV D

ADD T2

STORE X 

0 ADDRESS INSTRUCTION FORMAT

PUSH B

PUSH F

MUL

PUSH A

SUB

PUSH C

MUL

PUSH D

PUSH E

DIV

ADD

POP X 

3.
Differentiate between RISC and CISC.

[6]

4.
What factors cause microprogrammed control unit to be selected over hardwired control unit. Explain with relevant block diagram, how address of control memory is selected in microprogrammed control unit.

[3+7]

5.

Describes Flynn’s classification. Explain the control pipeline hazard and its solutions.

[4+6]

6.
Explain booth's multiplication hardware algorithm with diagram. Multiply - 5 *- 9 using Booth's multiplication algorithm.

[5+5]

7.
Draw the flowchart for division of floating point numbers .

[4]

8.
Draw the memory hierarchy. Explain direct cache mapping with its merit and demerits.

[2+6] 

9.
Differentiate between isolated input output and memory mapped input output. Describe DMA controller with suitable block diagram .

[4+6]

10.
Discuss about inter process synchronisation with the suitable mechanism?

[4]